AI enters chip design verification phase

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Cadence has rolled out its latest AI-powered electronics design automation (EDA) platform called Verisium, which promises to reduce the time and resources chipmakers spend on the verification process.

The Santa Clara, Calif.-based company said MediaTek and Samsung are among the first companies to use Verisium to identify bugs in system-on-chip (SoC) designs and diagnose the causes of problems.

Modern processors are made up of billions of transistors that must fit into squares of silicon as small as a fingernail. How everything is organized on the chip and how (and where) it is placed in a system impacts metrics like performance, power efficiency, and even cost. As a result, Cadence began integrating artificial intelligence into many of its software tools to automate more aspects of the IC design process.

Verisium is a complement to its platform Cerebrus Intelligent Chip Explorer for AI-enhanced implementation and Optimality Intelligent System Explorer for AI-powered system-level analysis.

A meticulous process

The purpose of verification is to identify and resolve design flaws in chips in a pre-engineered state. It is the final process of testing the quality of the design and that everything inside works as expected in a product.

The verification process usually begins once you have completed the chip design. The hardware is simulated with software code in a hardware description language (HDL) used to test the various building blocks of the SoC. The test bench in effect creates a virtual version of the SoC which can be supplied with signals. Subsequently, you can measure and evaluate the SoC’s responses to determine if the SoC or the internal IP is having issues.

Cadence said Verisium works with its existing verification engines: Palladium for emulation, Protium for prototyping, Xcelium for simulation, Jasper for formal verification, and its Helium virtual and hybrid studios.

Previously, you had to run each of these engines separately for each step of the verification process, which Cadence calls a “run once, one engine” approach. Verisium, on the other hand, leverages Big Data and AI to optimize multiple runs of multiple engines during the entire SoC design and verification campaign.

As SoC complexity continues to increase, the verification process tends to take more time and resources than any other silicon engineering task. And so, as Cadence says, verification is ripe for improvement using AI.

Verisium also runs on Cadence’s new “JedAI” platform, which aggregates large amounts of data from the chip design process, analyzes it to identify areas for improvement, and even stores it for future use.

Cadence said JedAI is a platform in the sense that its AI-powered offerings — Verisium, Cerebrus and Optimality — and third-party silicon lifecycle management systems sit on top of it. When it comes to using Verisium, its verification tools feed data from the verification process, ranging from waveforms, coverage and reports to log files, into the JedAI platform, where everything is stored and evaluated.

Then JedAI builds machine learning models and extracts other proprietary metrics from the data, sharing what it learns with the company’s Verisium to identify potential areas for improvement or root cause issues.

“As the size and complexity of chip design has increased exponentially over the past decade, the volume of design and verification data has also increased,” said Venkat Thanvantri, vice president of R&D. AI at Cadence. “Previously, we’ve seen that once a chip design project is complete, valuable data is discarded to make way for the next project. There are valuable learnings in legacy data, and the Cadence platform JedAI makes it easy for engineering teams to access these learnings and apply them to future designs.

Starter apps

Customers can start with multiple applications when using Verisium. Some of them leverage machine learning, both supervised and unsupervised, including reinforcement learning, while others do not.

  • Verisium automatic sorting: Creates machine learning models that help automate the repetitive task of sorting failures to find the worst ones. It does this by predicting and classifying test failures with common root causes.
  • Verisium SemanticDiff: Uses algorithms to compare source code revisions of IP building blocks or complete SoCs. The application categorizes these revisions and categorizes the ones that most disrupt system behavior to help identify potential bug hotspots.
  • Verisium WaveMiner: Applies artificial intelligence engines to analyze waveforms from multiple verification cycles and determine which signals, when, are most likely to represent the root cause of a test failure.
  • Verisium PinDown: Integrates with the Cadence JedAI platform and other industry standard tools to create machine learning models of source code changes, test reports and log files to predict source code records most likely to have introduced failures.
  • Verisium debugging: Natively integrated with the JedAI platform and other Verisium applications, this application uses AI for root cause analysis, as well as support for simultaneous and automatic comparison of passed and failed tests. The debugging solution ranges from IP to SoC and from single-run verification to multi-run verification.
  • Verisium Manager: Brings Cadence’s complete IP- and SoC-level verification management solution with verification scheduling, task scheduling, and multi-engine coverage on its JedAI platform. It uses artificial intelligence technologies to improve the efficiency of verification execution by data centers. This application integrates directly with other Cadence Verisium applications, opening the door to push-button deployment of the full Verisium platform from a unified browser-based management console.

AI time saver

Paul Cunningham, senior vice president and general manager of Cadence’s system and verification division, said Verisium will help chip companies make more informed decisions during the design and verification process. But the biggest impact seems to be on the productivity side.

The company said its customers are already using Verisium to triage failing tests more than 3x faster than before, with reductions in the time it takes to determine the root cause of failure by up to 75%.

Given that failure analysis and debugging accounts for 50% (or in some cases more) of the time chip companies spend on verification, Cadence claimed the AI-driven Verisium tool could lead to improvements productivity majors.

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