A multi-level analog IC design workflow for rapid performance estimation using model-based layout generators and structural models

Low power – high performance


How using model-based glitches and layout generators with SystemC-based parametric modeling accelerates analog IC design.

Designing analog ICs is a very difficult task because essential information is missing in the early design stages. Since simulating larger designs is extremely computationally expensive at lower levels of abstraction, conservative assumptions are usually applied, often resulting in suboptimal performance such as area and power consumption . In order to enable both early performance estimations and fast iteration cycles, we combined parasitic estimation from model-based layout generators with parameterizable SystemC-based modeling. As a result, we can calculate performance estimates considering the layout of a configurable capacitive pipeline ADC in a running time of about one minute per iteration. Using this estimate in a loop, we analyzed and optimized substantial parameters of a capacitor network to improve ADC performance.

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